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iSaSiLk 5.107 released!

13/12/2017

iSaSiLk 5.107 has improved its countermeasure against variants of the PKCS#1 Bleichenbacher attack and adds support for the Application Layer Protocol Negotiation (ALPN) extension!

IAIK-JCE 5.5 released!

29/08/2017

IAIK-JCE 5.5 fixes a signature algorithm name incompatibility in JSSE algorithm constraint checking, implements SHA-3 based signature and HMAC algorithms, and adds throughout support for using the IAIK provider without the necessity of installing it within the JCA/JCE Security framework.

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Our Clients


IAIK IP AES FPGA

This IP module is specialized for use on FPGA. The module makes use of the very efficient structure of CLBs for storing the intermediate value and results therefore in an area-efficient design. AES-128 encryption and decryption in ECB and CBC mode of operation is supported.

Features:

  • Functionality: AES-128, encryption & decryption
  • Mode of operation: CBC, ECB
  • Slices: 800 (Xilinx Virtex 4)
  • Clock Cycles/enc: 95 Max f (Xilinx Virtex 4): 150 MHz
  • Interface: AMBA-APB 32-bit

Deliverables:

  • VHDL, tcl-testbench (Modelsim, Cadence), scripts for synthesis & simulation

 Further technical and sales information:

Please contact sales@iaik.tugraz.at for any further information!

Prices:

Please see our price list.

 

 
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