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[iaik-ssl]cu|| hardware acceleration for RSA
we build a package that integrates AEP SSL acceleration hardware
(http://www.aep.ie) into our toolkit(s). these boards accelerate modulo
exponentiation. the integration package consists of two parts. the first
part is a wrapper that makes the AEP hardware accessible from Java. the
sencond part integrates the AEP hardware into our iSaSiLk toolkit using
the SecurityProvider concept of iSaSiLk. however, one can use it to
accelerate the RSA operation of IAIK JCE toolkit, because this package
implements an extended version of RSACipher that uses the hardware.
this integration package is based on IAIK JCE 3.0 and iSaSiLk (IAIK-SSL)
3.04, it will not work with older versions. applications based on
iSaSiLk will benefit from the hardware integration without any change.
the hardware integration is completely transparent. you will not even
need to recompile your application. if you have AEP hardware, you can
simply try if it brings better performance in your use-case.
we provide this package with source-code as is without any guarantees or
additional support. see it as a biggger demo for iSaSiLk ;-).
because of the fact that the wrapper is completely independent from the
SSL integration, you can use the wrapper alone to access AEP hardware
accelerators from within Java.
you can download it from our evaluation site
Karl Scheibelhofer, <mailto:Karl.Scheibelhofer@iaik.at>
Institute for Applied Information Processing and Communications (IAIK)
at Graz University of Technology, Inffeldgasse 16a, 8010 Graz, Austria,
http://www.iaik.at and http://jcewww.iaik.at
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